The present invention relates to circuitry for counting or dividing. More particularly, the present invention relates to frequency prescaler circuits. Still more particularly, the present invention relates to dual modulus prescaler circuits for use in frequency synthesizers.
Prescaler circuits for use in high-speed dividers, frequency synthesizers and the like are well known in the art. A dual modulus prescaler is a divider whose division ratio or modulus can be switched from one value to another by a control signal. Commonly known implementations of prescalers utilize a counter circuit consisting of series-coupled flip-flop circuits that are used to obtain an output whose frequency is a fraction of that of a clock signal. Thus, a prescaler can divide by a first factor when a control signal has a first state or by a second factor when the control signal has a second state. Aspects of prescaler circuits and component dual modulus dividers used in a variety of RF contexts are described generally in B. Razavi,RF Microelectronics, Prentice-Hall PTR, 1998, especially pp. 269-297.
Many electronic devices, including mobile radiotelephones operating in the 800-900 MHz and higher frequency bands require prescalers operating at correspondingly high frequencies under a variety of conditions. Further, many such applications of prescaler circuits place low power dissipation requirements for to enhance portability and extend period of use between battery recharges. In addition, prescalers for use in many portable devices advantageously operate at low supply voltage levels.
FIG. 1 shows a typical prior art prescaler circuit 100 comprising three sub-circuits: a synchronous dual-modulus divider (illustratively a divide by 4/5 divider) 105; a fixed-modulus divider (illustratively divide by 8) 110; and decode logic 115.
As suggested by its name, synchronous dual-modulus divider 105 will, depending on the state of divider control signal divc on path 135, divide an input frequency clock signal fin (applied on path 120 to each of three D-type flip-flops 145, 150 and 157) by either 4 or 5. Each of flip-flops 145, 150 and 157 has a Q and a/Q (Q-bar) output, and feedback paths from the Q outputs of flip-flops 150 and 157 to the D input to flip-flop 145 (input D1).
Fixed modulus divider 110 in FIG. 1 receives divided clock pulses fb from dual-modulus divider 105 over path 130 to flip-flop 180-1 and counts them in standard fashion using flip-flops 180-i, i=1, 2, 3. In particular, transitions of flip-flop 180-1 are triggered by rising edges of divided clock pulses on fb. Output fout appearing on path 125 is the desired divided output frequency signal. In selectively supplying binary state signals for divc, decode logic 115, including AND gates 160 and 165, receives inputs from flip-flops 180-i in fixed modulus divider 110 and a modulus control signal mc on lead 170.
In one application of the circuit of FIG. 1, operation as either a divide-by-32 or divide-by-33 circuit is achieved. Divide-by-32 operation is obtained if the dual-modulus divider 105 operates in divide-by-4 mode for eight cycles, accounting for 32 cycles of the input clock signal fin on path 120. These eight cycles of dual-modulus divider 105 comprise one full cycle of the fixed modulus divider 110 and, therefore, of prescaler 100. Divide-by-33 operation is obtained if dual-modulus divider 105 operates in divide-by-5 mode for one cycle (five cycles of input clock fin), and in divide-by-4 mode for seven cycles (28 cycles of fin), for a total of 33 cycles of fin. The eight cycles of dual-modulus divider 110 again comprise one full cycle of the fixed-modulus divider 100, and therefore of prescaler 100.
The divc signal on path 135 determines the mode of operation of the dual-modulus divider 105. If divc is in a first state, then dual-modulus divider 105 operates in a divide-by-4 mode, and if divc is in a second state, then dual-modulus divider 105 operates in a divide-by-5 mode. For proper operation, divc must be held in one of its two states for approximately one cycle of dual-modulus divider 105. In typical applications of prescaler 100 selection of divide-by-32 or divide-by-33 mode is performed by a circuit external to prescaler 100. This external circuit may be a programmable divider that receives output signal fout as its clock and generates modulus control signal mc on path 170. The mc signal will appear in one or the other of its states for the duration of one or more periods of fout. Decode logic 115 uses the mc signal and decodes the state of fixed modulus divider 110 to generate divc in a state corresponding to the state of mc for the required duration (approximately one cycle of dual-modulus divider 105).
FIGS. 2A and 2B are state transition diagrams for the divide-by-4 and divide-by-5modes of operation of divide circuit 105 of FIG. 1. In particular, each of these state transition diagrams show eight states represented by a three-bit sequence (Q1 Q2 Q3) associated with flip flops 145, 150 and 157, with the most significant bit (MSB) corresponding to the Q output of flip-flop 145 (Q1), the next bit corresponding to the Q output of flip-flop 150 (Q2), and the least significant bit (LSB) corresponding to the Q output of flip-flop 157 (Q3). The state machine reflected by FIGS. 2A and 2B is clocked by input clock signal fin on path 120 to synchronous divider 105.
Input control to the state machine is provided by divider control signal, divc, on path 135, with state machine transitions from one state to another during each clock period of the input signal occurring in response to the one-bit divc signal. Transitions are indicated in the FIGS. 2A and 2B by directional arrows labeled with divc values x, 0, or 1, where divc=x indicates xe2x80x9cdon""t care,xe2x80x9d divc=0 indicates divide-by-4 mode, and divc=1 indicates a divide-by-5 mode. Thus, for example, if divc=0 and flip-flops 145, 150 and 157 are in respective states 1,0,0 (Q1=1; Q2=Q3=0), then /Q2=1, the output of NAND gate 155 is 1, and a 1 is clocked into flip-flop 157 while flip-flops 145 and 150 have 1""s clocked inxe2x80x94thus giving rise to a new state of 111. But, if flip-flops 145, 150 and 157 exhibit a 110 state (Q1=1, Q2=1, and Q3=0), then the next state will be 111 regardless of whether divc is a 0 or a 1.
In the state transition diagrams of FIGS. 2A and 2B, crosshatched states are those from which transitions occur for the respective mode (divide by 4/5). The normal state transition path for the divide-by-4 mode (FIG. 2A) is: 111= greater than 011= greater than 001= greater than 101. Similarly, normal sequence of state transitions in the divide-by-5 mode is: 111= greater than 011 = greater than 001= greater than 100= greater than 110. Two of the eight states (010 and 000) are start-up states that are not present in the normal divide by 4 or divide by 5 paths.
FIG. 3 is a timing diagram for operation of prescaler 100 of FIG. 1 illustrating clocking inputs (fin), states traversed in respective divide-by-5 and divide-by-4 operating modes and the state of each of the fb and divc signals. The waveform for divc in FIG. 3 shows a maximum allowable delay for the transition from one state to another. In particular, it will be appreciated that, because divc is generated, in part, in response to states of fixed modulus divider 115, and because states of divider 115 depend, in turn, on fb, a maximum of one input clock cycle can be counted on as the period in which the divc signal will settle after a rising edge occurs in the fb signal.
Since divide-by-4/5 circuits are important elements of prescaler operation, considerable effort has been devoted to insure that reliable high-speed operation is achieved in this sub-circuit. It has also proven desirable to employ relatively lower performance circuit structures for the fixed-modulus divider 110 and decode logic 115 to realize advantages in current drain and, in some cases, reduced circuit area and manufacturing costs. Nevertheless, optimum operation of dual-modulus dividers can be degraded by timing limitations of these lower performance elements. Moreover, simply speeding up performance of fixed modulus divider and decoding elements will not only incur increased fabrication costs, but will also incur increased power usage.
Accordingly, there exists a need for high-speed prescaler architectures operating at low power levels and low supply voltage that realize benefits of optimized performance of high-speed dual modulus dividers.
Limitations of the prior art are overcome and a technical advance is made in accordance with the present invention, typical embodiments of which are described below.
In accordance with one illustrative embodiment of the present invention prior prescaler organizations are modified by avoiding reliance on transitions in a divider control signal occurring within relatively narrow tolerances. Moreover, such modifications are accomplished at no penalty in manufacturing costs or increased power consumption.
In accordance with an aspect of illustrative embodiments of the present invention dual modulus divider state transitions giving rise to incrementing of fixed-modulus divider states are selected to be independent of possible short-term changes in divider control inputs to the dual modulus divider. Thus, for example, it proves possible to constrain state transitions from certain critical states in a dual modulus divider to occur only prior to a period of insensitivity to short-term instabilities in a dual-modulus divider control signal.
In realizing such improved operation it proves advantageous to select an output signal from a dual modulus divider that ensures that there will be a subsequent time interval sufficient to realize desired stability of a modulus selection signal for the dual-modulus divider in its next divide cycle.